The present invention relates to an active load for use with emitter coupled logic type output circuits.
Load circuits currently used in emitter coupled logic outputs use either ordinary resistors to the negative supply voltage line (i.e. V.sub.EE) or a transistor in series with a resistor coupled to the emitter of both the true and complement emitter follower output transistors. Typically such loads add 20% to 30% to the power of most emitter coupled logic circuits. The loading of such circuits can be reduced by half by using a differential pair with a single transistor coupled to V.sub.EE with each output transistor in the collector circuit of one of the differential transistors. However, it is still highly desirable to further reduce the power consumption of such load circuits.
A more complex pull down or load circuit for ECL circuits is disclosed in U.S. Pat. No. 4,559,458 issued on Dec. 17, 1985 to Bing-Fong Ma. The Ma patent uses 13 components to load only one output. As far as power consumption is concerned, Ma connects 5 components to ground for one output. Each time a component connects to ground the D.C. power increases. The minimum voltage required to operate the Ma circuit is 3.7 volts. It is desirable for ECL circuits to be able to operate down to voltages less than 2 volts.
Accordingly, it is an object of the invention to provide an active load circuit for emitter coupled logic circuits which adds relatively little power to the emitter coupled logic circuit.